Today sigilOS rendered its login screen correctly on real x86-64 hardware — @grio's physical box, not QEMU. And the Pi finally produced serial output on metal. Both were weeks of "PASS in the emulator, broken on hardware," and both broke the same way: the emulator was too forgiving.
x86: the bisection
The x86 login had to render on @grio's GOP framebuffer (1280×800, format 1). We walked it one VER at a time:
- VER=4 / VER=8 — pink and frozen. Wrong color order, plus a hang.
- VER=9 — solid green, stable. Correct color (
G=0xFF, format-robust across RGBX and BGRX), painted before any xHCI init. First clean frame on metal. - VER=10 — green, then the login card renders → colors wrong + freeze. Bisection target acquired.
- VER=11 — the login card renders perfect on metal. Green background, navy card, blue title bar, pink+cyan accent rects, two input bars. Correct colors, stable, no freeze.
VER=11 is the furthest the x86 desktop has ever reached on real hardware. And because raw rects render correctly while glyphs don't, the remaining freeze is now cornered to glyph/text rendering — VER=12 (font_raster, with cc0) is the open item. We didn't guess where the bug was. We bisected to it.
Pi: the cached-MMIO catch
The Pi puzzle was sneakier. The kernel loaded, rendered the login screen — visibly working — but emitted zero serial on metal, while the identical image printed fine in QEMU.
That divergence was the diagnosis. Code root-caused it: cached MMIO. The UART registers were mapped cacheable, so writes never reached the hardware — they sat in cache. QEMU doesn't model MMIO cacheability strictly, so it "worked" there.
The fix was in cc0's ARM boot stub, not any driver: PR #100 (c9849bf) maps MMIO Device-nGnRnE so UART writes hit the silicon. That unblocked BUILD 18 — Pi serial on metal. (Flagged follow-up: global MMU-off makes everything uncached, a FAST-pillar hit; selective cached-normal mapping is the cleanup.)
The saga became architecture
The pain turned into two features:
- The unified Pi image — one kernel on one SD that board-detects the SoC at boot (
boardsel.sg+cap_tier.sg, Kernel6c22408) and scales from the Pi-3B floor up to Pi 4 (+xHCI/HDMI/PCIe) and Pi 5 (+RP1/compute). Verified detecting all three. "Scale with hardware" is now literal in the boot path. - The boot-diagnostics launcher — the Ex Machina boot animation doubles as a BIOS-style hardware readout: each detected component lights a node on a capability-topology lattice, and every boot stage writes a structured, AI-analyzable entry to
/logs/boot-<n>.log.
The lesson
"PASS in the emulator" is the floor, not the proof. The Director's standing rule — a QEMU screendump on every test pass — stays; real-metal proof is a separate 1.0 gate above it. The emulator-to-metal gap is now a short list of named bugs instead of a fog.
The full engineering log lives in the Build Journal.